pub struct ControllerPort { /* private fields */ }Expand description
The controller and memory-card port.
Implementations§
Trait Implementations§
Source§impl Debug for ControllerPort
impl Debug for ControllerPort
Source§impl Transport for ControllerPort
impl Transport for ControllerPort
Source§fn set_control(&mut self, value: u16)
fn set_control(&mut self, value: u16)
Write the control register.
Source§fn select_with(&mut self, port: Port, arm_ack_irq: bool)
fn select_with(&mut self, port: Port, arm_ack_irq: bool)
select with the /ACK interrupt armed when
arm_ack_irq is set, so STAT latches each pulse. Only a diagnostic
pacing wants that.Source§fn reset(&mut self)
fn reset(&mut self)
Reset the port’s UART. A deselect alone need not cancel a late reply
still in the shifter, so a failed transaction ends with this.
Source§fn drain_receive(&mut self)
fn drain_receive(&mut self)
Pop up to a few stale bytes so the next reply lines up with the
first byte of the transaction. Bounded, so a stuck “RX not empty” flag
cannot spin forever.
Source§fn delay(&mut self, spins: u32)
fn delay(&mut self, spins: u32)
Burn time with
spins status reads, which the compiler cannot remove.Source§fn wait_status_set(&mut self, mask: u32, spins: u32) -> bool
fn wait_status_set(&mut self, mask: u32, spins: u32) -> bool
Spin until any bit of
mask is set in the status register, at most
spins reads after the first. false on timeout.Source§fn wait_status_clear(&mut self, mask: u32, spins: u32) -> bool
fn wait_status_clear(&mut self, mask: u32, spins: u32) -> bool
Spin until every bit of
mask is clear in the status register, at most
spins reads after the first. false on timeout.Source§fn begin(&mut self, port: Port, timing: Timing) -> bool
fn begin(&mut self, port: Port, timing: Timing) -> bool
Start a transaction: select
port, wait out the setup time, drop
stale bytes, and wait for an /ACK left asserted by an aborted
transaction to release, so it is not counted as the first byte’s. Read more