Trait Transport 

pub trait Transport {
    // Required methods
    fn status(&mut self) -> u32;
    fn receive(&mut self) -> u8;
    fn transmit(&mut self, byte: u8);
    fn set_mode(&mut self, value: u16);
    fn set_baud(&mut self, value: u16);
    fn set_control(&mut self, value: u16);

    // Provided methods
    fn select(&mut self, port: Port) { ... }
    fn select_with(&mut self, port: Port, arm_ack_irq: bool) { ... }
    fn deselect(&mut self) { ... }
    fn reset(&mut self) { ... }
    fn drain_receive(&mut self) { ... }
    fn delay(&mut self, spins: u32) { ... }
    fn wait_status_set(&mut self, mask: u32, spins: u32) -> bool { ... }
    fn wait_status_clear(&mut self, mask: u32, spins: u32) -> bool { ... }
    fn begin(&mut self, port: Port, timing: Timing) -> bool { ... }
    fn finish(&mut self, succeeded: bool) { ... }
    fn exchange(
        &mut self,
        byte: u8,
        is_last: bool,
        timing: Timing,
    ) -> Result<u8, ExchangeError> { ... }
}

The six accesses the transport makes to the port, and the transaction steps built on them.

ControllerPort implements it on the registers. Host tests implement it on a model of a pad or a card, so the production timing code runs under test unchanged.

Required Methods

fn status(&mut self) -> u32

Read the status register.

fn receive(&mut self) -> u8

Pop one received byte.

fn transmit(&mut self, byte: u8)

Start shifting one byte out.

fn set_mode(&mut self, value: u16)

Write the mode register.

fn set_baud(&mut self, value: u16)

Write the baud-rate reload.

fn set_control(&mut self, value: u16)

Write the control register.

Provided Methods

fn select(&mut self, port: Port)

Configure the port for 250 kHz, 8N1 and assert /CS on port.

The /ACK interrupt is left disarmed: arming it disturbed real transfers (the SCPH-1200 stopped answering, a clone’s bytes corrupted), so the transport watches the live /ACK level in STAT instead.

fn select_with(&mut self, port: Port, arm_ack_irq: bool)

select with the /ACK interrupt armed when arm_ack_irq is set, so STAT latches each pulse. Only a diagnostic pacing wants that.

fn deselect(&mut self)

Release /CS, which resets the attached device’s state machine.

fn reset(&mut self)

Reset the port’s UART. A deselect alone need not cancel a late reply still in the shifter, so a failed transaction ends with this.

fn drain_receive(&mut self)

Pop up to a few stale bytes so the next reply lines up with the first byte of the transaction. Bounded, so a stuck “RX not empty” flag cannot spin forever.

fn delay(&mut self, spins: u32)

Burn time with spins status reads, which the compiler cannot remove.

fn wait_status_set(&mut self, mask: u32, spins: u32) -> bool

Spin until any bit of mask is set in the status register, at most spins reads after the first. false on timeout.

fn wait_status_clear(&mut self, mask: u32, spins: u32) -> bool

Spin until every bit of mask is clear in the status register, at most spins reads after the first. false on timeout.

fn begin(&mut self, port: Port, timing: Timing) -> bool

Start a transaction: select port, wait out the setup time, drop stale bytes, and wait for an /ACK left asserted by an aborted transaction to release, so it is not counted as the first byte’s.

false means the line never released. Call finish either way.

fn finish(&mut self, succeeded: bool)

End a transaction: release /CS, and after a failed one reset the UART as well. The next select restores mode and baud.

fn exchange( &mut self, byte: u8, is_last: bool, timing: Timing, ) -> Result<u8, ExchangeError>

Clock one byte and wait for the device’s /ACK.

Waits for TX ready, writes byte, and watches the live /ACK level while the reply shifts in, so a pulse that ends before the reply arrives is not missed. Unless is_last (the final byte of a packet is never acknowledged), it then waits for /ACK to assert if it has not yet, and to release, before the next byte may go. RX-ready alone only says the byte arrived, not that the device is ready for another.

No control-register write happens mid-transaction.

Implementors

impl Transport for ControllerPort