pub struct Gte { /* private fields */ }Expand description
Full GTE state. Field grouping matches the PSX register map:
vectors / FIFOs / accumulators in data-prefixed fields, matrices
and translations in ctrl-prefixed fields. The MFC2/MTC2 paths
pack and unpack these into 32-bit views.
Implementations§
Source§impl Gte
impl Gte
Sourcepub fn command_cycles(instr: u32) -> u32
pub fn command_cycles(instr: u32) -> u32
Real-hardware cycle latency of the GTE command encoded in instr
(the bottom six bits select the function), or 0 for encodings that
decode as nops. Lets a CPU model charge the latency it stalls on
when a GTE result register is read before the op completes.
Sourcepub fn new() -> Self
pub fn new() -> Self
Construct a freshly-reset GTE – all registers cleared. Real hardware powers on with garbage, but the BIOS zeroes the lot before first use, so we save a redundant write by starting clean.
Sourcepub fn profile_snapshot(&self) -> GteProfileSnapshot
pub fn profile_snapshot(&self) -> GteProfileSnapshot
Current monotonic GTE diagnostic counters.
Sourcepub fn read_data(&self, idx: u8) -> u32
pub fn read_data(&self, idx: u8) -> u32
MFC2 view of data register idx. Mirrors what the CPU sees on
mfc2 rt, $rd.
Sourcepub fn write_data(&mut self, idx: u8, value: u32)
pub fn write_data(&mut self, idx: u8, value: u32)
MTC2 view of data register idx.
Sourcepub fn read_control(&self, idx: u8) -> u32
pub fn read_control(&self, idx: u8) -> u32
CFC2 view of control register idx.
Sourcepub fn write_control(&mut self, idx: u8, value: u32)
pub fn write_control(&mut self, idx: u8, value: u32)
CTC2 view of control register idx.
Sourcepub fn execute_with_stale_v0x(&mut self, instr: u32, stale_x: i16)
pub fn execute_with_stale_v0x(&mut self, instr: u32, stale_x: i16)
Execute one COP2 function with the HWB-010 MTC2-commit hazard
injected: the first transform row reading V0 sees stale_x as V0.x
(the value held before the in-flight MTC2 VXY0 write), while later
rows see the fresh register.
Silicon-measured: six exact arithmetic confirmations across two live
hardware captures, HWB-009 and HWB-010.
Sourcepub fn execute_op_with_stale_ir3(&mut self, instr: u32, stale_ir3: i16)
pub fn execute_op_with_stale_ir3(&mut self, instr: u32, stale_ir3: i16)
Execute OP with an MTC2 IR3 value still committing during its first
sequential MAC row. MAC1 sees stale_ir3; MAC2/MAC3 see current IR3.