pub const fn fault_resume_pc(cause: u32, epc: u32, badvaddr: u32) -> Option<u32>Expand description
Where psx-rt’s exception handler resumes after a fault (any exception
but an interrupt), or None where it halts. badvaddr is COP0
BadVAddr.
BREAK (the shipping form of panic=immediate-abort), an instruction bus
error and a misaligned instruction fetch (AdEL with BadVAddr == EPC)
halt. So does any fault with [psx_hw::cop0::CAUSE_BD] set: the faulting instruction
sat in the delay slot of the branch at EPC, which has already run, so
epc + 4 would run the faulting instruction again as if the branch had
fallen through, and resuming where the branch goes would take decoding
it, handler code every game carries for a path only a bug reaches.
Every other fault is stepped over (epc + 4) and counted, unless
STRICT_FAULTS is set, in which case every fault halts. The
handler’s assembly makes exactly this decision; before halting it
records Cause, EPC and BadVAddr (fault_cause, fault_pc,
fault_bad_address).