Module dma 

DMA controller.

The PS1 has 7 DMA channels (MDEC in, MDEC out, GPU, CD-ROM, SPU, expansion, ordering-table clear). Each channel has an address, a size and a control register at fixed 16-byte strides, plus a global enable and a global interrupt register. The addresses and bit layouts live in [psx_hw::dma].

Modules

raw

Single-register writes for silicon probes and drivers that need a store order other than start’s.

Structs

Transfer

The three per-channel register values that describe one transfer.

Enums

Channel

Channel index 0..=6 in the order the DMA controller presents them.

Constants

DEFAULT_SPINS

Spin budget for one DMA completion wait. Comfortably longer than the largest legitimate transfer (a full-screen VRAM upload) and short enough that a wedged channel returns control inside a frame.

Functions

abort

Clear ch’s control register, dropping its START bit, so the channel can be re-armed: on silicon a CHCR write to a channel whose START is still latched is ignored, which is how one wedged kick used to poison every later transfer on the channel.

address

Read the channel’s RAM address register.

clear_ordering_tableDeprecated

OrderingTableClearDma::clear_table on a token the caller does not hold.

compiler_barrier

Compiler-only barrier: ordinary RAM accesses are not moved across it in either direction, so stores before it land before an MMIO store after it and accesses after it follow an MMIO read before it.

control

Read the channel’s control register.

enable_channel

Enable a channel without disturbing the others.

is_busy

True while the channel is busy with an in-flight transfer.

set_bcr_manual^⚠Deprecated

Write the size register in manual / linked-list mode: just a 16-bit word count.

set_chcr^⚠Deprecated

Write the control register. Starts the transfer if CHCR_START is set.

set_madr^⚠Deprecated

Write the channel’s RAM address register.

size_blocks

Size word for block sync: block_count blocks of block_size words.

size_words

Size word for manual or linked-list sync: a 16-bit word count (linked-list mode ignores it, but silicon wants it written).

start^⚠

Program channel ch with transfer and start it.

wait_done

Bounded completion wait. false means the channel was still busy when the budget ran out, i.e. the transfer is wedged and the caller must not assume its data landed.

wait_or_abort

End a transfer started with start: wait_done; if the budget runs out, abort the channel and wait again, within the same budget, for it to read idle; then a compiler barrier so the caller’s next RAM access to the buffer is not moved before the completion read (the barrier emits no instruction). false means the data did not all land.