Module encoding 

The COP2 instruction encodings the wrappers emit (psx_hw::gte). GTE (COP2) instruction encodings.

The geometry engine is driven by two kinds of instruction: register moves (mfc2, mtc2, cfc2, ctc2) and function commands (RTPS, MVMVA, …), which are COP2 instructions with bit 25 set. Both are built here as const fns so a guest can emit them as .words the assembler need not know, and a host tool can decode or generate the same words.

  bits 31..26 = 0x12 (COP2)
  bit  25     = 1 for a function command; 0 for a register move
  bit  19     = sf, fraction shift (commands)
  bits 18..17 = mx, MVMVA matrix select
  bits 16..15 = vx, MVMVA vector select
  bits 14..13 = cv, MVMVA translation select
  bit  10     = lm, IR lower-bound mode
  bits  5..0  = function number

Reference: nocash PSX-SPX “GTE Opcode Summary” and “GTE Coprocessor Opcodes”.

Modules

command

Function commands as the SDK issues them: sf set where the command takes it, lm clear.

Enums

Matrix

MVMVA matrix select (mx).

Translation

MVMVA translation select (cv).

Vector

MVMVA vector select (vx).

Constants

COMMAND

Every function command starts with this prefix: COP2 with bit 25 set.

COP2

The COP2 major opcode, 010010, in bits 31..26.

LM

lm: clamp IR1..IR3 at 0 instead of -0x8000.

PREFIX_SHIFT

Position of the command prefix COMMAND in a word: the top seven bits.

SF

sf: shift the product right by 12 (clear: no shift).

Functions

cfc2

cfc2 rt, rd: copy GTE control register rd into CPU register rt.

ctc2

ctc2 rt, rd: copy CPU register rt into GTE control register rd.

is_command

Whether word is a GTE function command (top seven bits 0100101).

mfc2

mfc2 rt, rd: copy GTE data register rd into CPU register rt.

mtc2

mtc2 rt, rd: copy CPU register rt into GTE data register rd.

mvmva

MVMVA with the given selects, sf and lm clear; OR in SF and LM as needed.