Module mdec 

MDEC driver: table upload, decode command, DMA0 in, DMA1 out.

Mdec owns the two DMA channels that feed and drain the decoder; every step that starts one is a method on it.

Decode protocol, as commercial players drive it:

1. Mdec::reset once, then Mdec::load_tables (quantization + IDCT tables). Neither assumes the MDEC reacts at once: see “Reset latency” below.
2. Per frame, Mdec::decode_start writes the decode command (output depth + run-length word count) to MDEC0 and kicks DMA0 with the whole run-length buffer. It does not wait: the MDEC throttles DMA0 as its output FIFO fills.
3. Mdec::read_column pulls one 16-pixel-wide column of decoded macroblocks over DMA1 (macroblocks come out in the order the bitstream stores them: top to bottom, then left to right), which the caller uploads to VRAM.
4. Mdec::decode_finish confirms DMA0 drained.

Every wait is bounded (psx_io::dma::wait_done), and every kick aborts the channel first, per the SDK rule for silicon DMA wedges.

Reset latency

On a PAL SCPH-9002 the MDEC does not finish a reset within the next bus access: the status read straight after writing the reset still shows the state from before it (0x6401_0000: busy, data-in full), where the SuperStation One FPGA and PSoXide already read the documented reset state. Writing the DMA-request enable right behind the reset, as this driver used to, left the table upload waiting on DMA0 forever on that console while both of the others played the movie. So Mdec::reset waits for the reset to settle before enabling requests, and Mdec::load_tables checks that the MDEC actually raised its data-in request (status bit 28) after each command, re-writing the enable if it did not, and falls back to CPU writes when DMA0 still will not take the table.

Structs

Mdec

The MDEC’s driver: it owns the two DMA channels that feed and drain it, so every decode step that starts one is a method here and the borrow checker sees a second decoder.

Tables

How Mdec::load_tables got the tables in.

Constants

DMA_BLOCK_WORDS

DMA block size the MDEC channels use, in words.

DMA_SPINS

Spin budget for one table upload or column transfer.

SETTLE_SPINS

Spin budget for one status wait (reset settle, request, FIFO room). The console settles a reset in tens of cycles; this is a few ms.

Statics

QUANT_WORDS

Luma then chroma table, zigzag order, as the 32 words command 2 takes.

SCALE_WORDS

The IDCT matrix for MDEC command 3, generated from the DCT basis in crate::idct.

Functions

load_tablesDeprecated

Upload the standard quantization tables and the IDCT basis.

resetDeprecated

Reset the MDEC and enable its DMA requests.

status

Raw MDEC1 status word.